A Reconfigurable Digital Decimation Filter Design for a Cascade 2-2 Sigma-Delta Analog-to-Digital Converter

This paper presents a reconfigurable digital design of filtering and decimation for a cascade 2-2 sigmadelta ( ) analog-to-digital converter (ADC). The ADC reconfigures its MASH (Multi-Stage-NoiseShaping) topology and building blocks in order to adapt the bandwidth requirements to diverse standard specifications. This reconfigurable design is composed by a logic cancellation of the total first stage quantization error, a 5 order CIC decimation filter followed by a Finite Impulse Response (FIR) compensator to correct the pass-band attenuation due to the CIC filter and a half-band FIR to reduce the transition band response. The complete high-level design was simulated in Matlab/Simulink environment and the hardware implementation of this design was coded with VHDL using optimization techniques for computational resources reduction aiming to reduce area and power consumption for future standard cell implementation. At this time, the complete design was validated and prototyped in a Stratix II FPGA device.